Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

Methods of preparing a dispersion of colloidal nanocrystals (NCs) for use as NC thin films are disclosed. A dispersion of NCs capped with ligands may be mixed with a solution containing chalcogenocyanate (xCN)-based ligands. The mixture may be separated into a supernatant and a flocculate. The flocculate may be dispersed with a solvent to form a subsequent dispersion of NCs capped with xCN-based ligands.

Methods of forming colloidal nanocrystal (NC)-based thin film devicesare disclosed. The methods include the steps of depositing a dispersion of NCs on a substrate to form a NC thin-film, wherein at least a portion of the NCs is capped with chalcogenocyanate (xCN)-based ligands; and doping the NC thin-film with a metal.

A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90 with respect to the substrate.

A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.

Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.

A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures.

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising N.sub.w nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets N.sub.w, width W.sub.w,i, of the nanowire/nanosheet number i, i being an integer from 1 to N.sub.w, thickness of the nanowire/nanosheet H.sub.w,i, number i, i being an integer from 1 to N.sub.w, corner radius R.sub.w,i of the nanowire/nanosheet number i, i being an integer from 1 to N.sub.w, R.sub.w,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage .sub.T given by .sub.T=k.sub.BT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.