A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.

Nanochannel arrays that enable high-throughput macromolecular analysis are disclosed. Also disclosed are methods of preparing nanochannel arrays and nanofluidic chips. Methods of analyzing macromolecules, such as entire strands of genomic DNA, are also disclosed, as well as systems for carrying out these methods.

A method for fabricating a nanopore at a particular location in a membrane includes controlling a dielectric strength of the membrane at a particular location on the membrane while applying one of an electric potential or an electric current to the membrane, monitoring an electrical property across the membrane while one of the electric potential or the electric current is being applied across the membrane, detecting an abrupt change in the electrical property across the membrane while one of the electric potential or the electric current is being applied across the membrane; and removing the electric potential or the electric current from the membrane in response to detecting the abrupt change in the electrical property.

The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities.

A method for manufacturing a dual-cavity structure and a dual-cavity structure, including: etching on a semiconductor substrate to form a first trench array, tops of the first trench array being separated from each other and bottoms thereof being communicated with each other to form a first cavity; growing a first epitaxial layer on the semiconductor substrate on which the first trench array is formed, to cover the first trench array by the first epitaxial layer; etching on the first epitaxial layer to form a second trench array; tops of the second trench array being separated from each other and bottoms thereof being communicated with each other to form a second cavity; growing a second epitaxial layer on the first epitaxial layer on which the second trench array is formed; and etching the first epitaxial layer and the second epitaxial layer to form a straight groove.

Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

An electronic component comprises a substrate including a main surface on which a functional unit is formed and a cap layer defining a cavity enclosing and covering the functional unit. The cap layer is provided with holes communicating an inside of the cavity with an outside of the cavity. A resin layer covers the cap layer and the main surface and includes one or more bores and a solder layer having a thickness less than a thickness of the resin layer disposed within the one or more bores.

A method of fabricating an electronic component includes forming a functional unit on a main surface of a substrate, forming a sacrificial layer covering the functional unit on the main surface, forming a cap layer covering the sacrificial layer, the cap layer forming a periphery enclosing the cavity on the main surface, forming holes through the cap layer, forming a cavity by removing the sacrificial layer using a wet etching process through the holes, the holes including a peripheral hole communicating an inside of the cavity with an outside of the cavity along the main surface, and forming a first resin layer covering the cap layer and the main surface.

A method for assembling colloidal particles onto a substrate surface through fluid transport. The method comprises placing a first fluid placed adjacent to the substrate surface, applying a colloidal dispersion on top of the first fluid layer and removal of the first fluid layer. The method is extremely versatile, and is especially useful in depositing colloidal materials in high aspect ratio channels and vias without the need for prior treatment of the surface.

A neural lattice device includes a substrate having formed therein one or more wells and one or more supply ducts. A channel network includes one or more channels configured to establish fluid communication among the at least one well and the at least one supply duct. A reservoir is coupled to the substrate and configured to hold a fluid, and a cover is disposed against an upper surface of the substrate and configured to hermetically seal the wells, the supply ducts and the channel network.