A print head drive circuit outputs an output signal from a terminal electrically coupled to a low voltage logic signal input terminal to which a low voltage logic signal is input and has a first mode in which the print head drive circuit controls a print head to execute reading processing of reading information stored in a memory and not to execute ejection control processing of controlling whether or not to supply a high voltage signal to an ejecting portion group by switching a switch group in accordance with the output signal and a second mode in which the print head drive circuit controls the print head not to execute the reading processing and to execute the ejection control processing in accordance with the output signal.

A method of forming a print head, by forming a heater chip. Via zones having peripheries are defined on a substrate, with heaters formed along the entire peripheries of the via zones. Traces that electrically connect to each of the heaters are formed. In some embodiments, the heater chip is then stored for a period of time. After storing the heater chip, vias are formed in only a selected portion of the via zones, which is a subset of the via zones. A channel layer is formed on the heater chip by forming a first layer on the heater chip. Flow channels are formed in the first layer from the vias to only those heaters on the heater chip that are disposed along the selected portion of the via zones. Bubble chambers are formed in the first layer around only those heaters on the heater chip that are disposed along the selected portion of the via zones. A nozzle plate in formed on the channel layer by forming a second layer on the first layer, and forming nozzles in the second layer above only those heaters on the heater chip that are disposed along the selected portion of the via zones.

A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.

An element substrate is provided with a fuse memory configured to store information in response to having a voltage applied thereto, a first switch configured to switch whether or not to energize the fuse memory, a resistance element, a second switch configured to switch whether or not to energize the resistance element, a first node connected to the fuse memory and the resistance element, and a second node configured to supply power to the first node from outside. Regarding the element substrate, electric charge that remains at the first node is discharged by allowing, before allowing the first switch to energize the fuse memory, the second switch to energize the resistance element from the first node.

In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board.

The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.

A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board.