B41J2202/17

LIQUID EJECTION HEAD AND LIQUID EJECTION APPARATUS
20240217234 · 2024-07-04 ·

A liquid ejection head includes a print element substrate having an ejection surface on which an ejection port corresponding to a print element for ejecting liquid is formed and a plurality of ejection port arrays formed of a plurality of the ejection ports are formed and a protective member having a plurality of openings and placed on the print element substrate so that the plurality of openings and the plurality of ejection port arrays are aligned so as to correspond to each other, and one or more print element number identifiers for identifying a print element number assigned to the print element are at a plurality of locations above the ejection port arrays and near an opening on the protective member.

Fluid ejection devices including a first memory and a second memory

An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.

Element substrate

A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.

Control device and method for controlling element substrate
12036798 · 2024-07-16 · ·

An element substrate is provided with a fuse memory configured to store information in response to having a voltage applied thereto, a first switch configured to switch whether or not to energize the fuse memory, a resistance element, a second switch configured to switch whether or not to energize the resistance element, a first node connected to the fuse memory and the resistance element, and a second node configured to supply power to the first node from outside. Regarding the element substrate, electric charge that remains at the first node is discharged by allowing, before allowing the first switch to energize the fuse memory, the second switch to energize the resistance element from the first node.

PRINTING APPARATUS AND CONTROL METHOD THEREOF

According to an embodiment of the present invention, to improve processing performance, a printing apparatus that performs printing by using a printhead formed by a plurality of headchips includes one CPU, a table configured to store processing contents set by the CPU, and a plurality of processing units configured to process, in parallel, printing data to be used in each headchip by commonly using the table and in accordance with the processing contents set in the table. In addition, the apparatus includes a plurality of control units configured to wait for the completion of the processing of each processing unit, synchronize the plurality of processing units for next processing, and cause each of the processing units to execute the next processing in accordance with the processing contents set in the table.

Authentication value for a fluid ejection device

A fluid ejection device includes a plurality of analog devices, and a storage element storing an authentication value based on electrical characteristics of a subset of the plurality of analog devices.

SEMICONDUCTOR APPARATUS, LIQUID DISCHARGE HEAD SUBSTRATE, LIQUID DISCHARGE HEAD, AND LIQUID DISCHARGE APPARATUS
20180281390 · 2018-10-04 ·

An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.

Fluid ejection devices including a memory

An integrated circuit to drive a plurality of fluid actuation devices includes a fire line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the fire line and a first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to a second side of a respective memory element of the plurality of memory elements.

Printhead with a number of memristors and inverters

A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The print head also includes a number of memristor cells. Each memristor cell includes a memristor to store data, a voltage divider serially connected to the 116 memristor cell, and an inverter connected in parallel with the number of memristor cells and the voltage divider.

Printhead having a number of single-dimensional memristor banks

A printhead having a number of single-dimensional memristor banks is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The printhead also includes a number of single-dimensional memristor banks. Each memristor bank includes a number of memristors arranged in a single dimension and a number of serially-connected de-multiplexers to selectively activate a target memristor of the memristor bank. The number of serially-connected de-multiplexers is equal to the number of memristors and an output of at least one de-multiplexer is an input into a subsequent de-multiplexer.