The disclosure provides a multi-junction solar cell structure and the manufacturing method thereof, comprising a first photovoltaic structure and a second photovoltaic structure; wherein at least one of the first photovoltaic structure and the second photovoltaic structure comprises a discontinuous photoelectric converting structure.

Methods of fabricating solar cells using simplified deposition processes, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell involves loading a template substrate into a deposition chamber and, without removing the template substrate from the deposition chamber, performing a deposition method. The deposition method involves forming a first silicon layer on the template substrate, the first silicon layer of a first conductivity type. The deposition method also involves forming a second silicon layer on the first silicon layer, the second silicon layer of the first conductivity type. The deposition method also involves forming a third silicon layer above the second silicon layer, the third silicon layer of a second conductivity type. The deposition method also involves forming a solid state doping layer on the third silicon layer, the solid state doping layer of the first conductivity type.

An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having side areas covered by a shaped body; at least one via including an electrically conductive material; and at least one electrically conductive connection electrically conductively connected to the semiconductor chip and the via, wherein the via is laterally spaced part from the semiconductor chip; the via includes a contact pin, the contact pin including an electrically conductive material; and the contact pin is laterally completely enclosed by the shaped body.

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

Examples of a substrate processing apparatus includes a chamber configured to contain a stage, a light receiving device configured to receive light inside the chamber, and a substrate transfer apparatus that includes a shaft and a rotation arm configured to rotate with rotation of the shaft and is configured to supply a plurality of light beams having different amounts of light to the light receiving device.

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

A method for time constraint management at a manufacturing system is provided. A first request to initiate a set of operations to be run at the manufacturing system is received. The set of operations include one or more operations that each have one or more time constraints. A first set of candidate substrates to be processed during the set of operations is determined. A first simulation of the set of operations for the first set of candidate substrates is run over a first period of time. The simulation generates a first simulation output indicate a first number of candidate substrates that were successfully processed during each of the simulated set of operations to reach the end of the first time period. The set of operations is initiated at the manufacturing system to process the first number of candidate substrates over the first time period.

A method of forming an electrode pattern includes: forming, on a base material, a seed layer having a pattern corresponding to the electrode pattern; forming an organic material layer on the seed layer; producing an electrode layer transfer sheet by forming an electrode layer on the organic material layer via an electroplating process using the seed layer as a seed; disposing the electrode layer transfer sheet on a substrate on which the electrode pattern is to be formed such that the electrode layer is in contact with the substrate and pressure bonding the electrode layer to the substrate; and in a state in which the electrode layer is pressure bonded to the substrate, removing the base material along with the organic material layer and the seed layer to transfer the electrode layer to the substrate.

Embodiments of the present invention may include single crystal silicon solar cell structures with epitaxially deposited silicon device layers with deep junction(s). In some embodiments, the single crystal silicon solar cell structures may comprise a moderately doped, thick (greater than 10 microns), epitaxially deposited silicon emitter layer. In some embodiments, the single crystal silicon solar cell structures may comprise moderately doped, thick (greater than 10 microns), epitaxially deposited FSF layers. The moderate doping reduces electron-hole recombination within the FSF and emitter layers and causes smaller bandgap narrowing and reduced Auger recombination compared to prior art devices which typically have more heavily doped layers, and the thicker FSF and emitter layers than typically used in prior art devices assist in having a desirable sheet resistance for the solar cell front and back surface, as measured prior to front side and back side metallization.

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.