A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D.sub.1 at a top surface, a second dimension D.sub.2 at a bottom surface, and a third dimension D.sub.3 at a location between the top surface and the bottom surface, and wherein each of D.sub.1 and D.sub.2 is greater than D.sub.3.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a nanostructure over the fin. The semiconductor device structure includes a gate stack wrapping around an upper portion of the fin and the nanostructure. The semiconductor device structure includes an inner spacer between the fin and the nanostructure. The semiconductor device structure includes a film in the inner spacer. A first dielectric constant of the film is lower than a second dielectric constant of the inner spacer. The semiconductor device structure includes a low dielectric constant structure in the film.

A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.

In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.