A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

A semiconductor device includes a substrate; an active region extending in a first, horizontal, direction on the substrate, and including a first active pattern at a first height above a bottom surface of the substrate in a vertical direction and having a first width in a second, horizontal, direction, a second active pattern having a second width in the second direction different from the first width, and a transition active pattern connecting the first active pattern to the second active pattern; gate structures intersecting the active region each gate structure extending in the second direction across the substrate; source/drain regions disposed on sides of the gate structures, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain region disposed on the transition active pattern. Each of the source/drain regions is disposed on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer disposed on the first epitaxial layer, at a second height above a bottom surface of the substrate in a vertical direction, a first sidewall thickness of the first epitaxial layer of the first source/drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source/drain region in the first direction, at the second height, thicknesses of opposing sidewalls of the first epitaxial layer of the transition source/drain region in the first direction are different, and a vertical level of a lowermost end of the second epitaxial layer of the first source/drain region, a vertical level of a lowermost end of the second epitaxial layer of the second source/drain region, and a vertical level of a lowermost end of the second epitaxial layer of the transition source/drain region are different from each other.

A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

Transistors and methods of forming the same include forming a fin having an active layer between two sacrificial layers. A dummy gate is formed over the fin. Spacers are formed around the dummy gate. The dummy gate is etched away to form a gap over the fin. Material from the two sacrificial layers is etched away in the gap. A gate stack is formed around the active layer in the gap. Source and drain regions are formed in contact with the active layer.

We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation. In an example embodiment, the magnetic electrodes have a substantially identical footprint that can be approximated by an ellipse, with the short axes of the ellipses being collinear and the edge-to-edge separation between the ellipses being smaller than the size of the short axis. In some embodiments, the magnetic electrodes may have relatively small tapers that extend toward each other from the ellipse edges in the constriction area between the electrodes. Some embodiments may also include an active element inserted into the gap between the tapers and electrical leads connected to the magnetic electrodes for passing electrical current through the active element. When subjected to an appropriate external magnetic field, the magnetic electrodes can advantageously be magnetized to controllably enter parallel and antiparallel magnetization states.

A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.

A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.