A semiconductor device may include a well region disposed in a substrate, an impurity injection region disposed in the well region, an active fin on the well region, a lower insulating layer covering the impurity injection region and the active fin, and a connection pattern provided to penetrate the active fin and connected to the well region. The substrate and the impurity injection region may have a first conductivity type, and the well region may have a second conductivity type different from the first conductivity type. An uppermost portion of the impurity injection region may be in direct contact with the lower insulating layer.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

A bipolar transistor is capable of reducing variations in electrical characteristics. A bipolar transistor 100 includes: a collector region 150 which is a predetermined region in a P-type semiconductor substrate 110; a base region 140 which is formed within the collector region 150 and is an N-type well region; a polysilicon 130 formed on the base region 140 via an insulating film 131 and having an outer periphery, as viewed in a plan view, in a rectangular ring shape; and a P-type emitter region 120 surrounded by the polysilicon 130 and formed within the base region 140. The polysilicon 130 includes an extension portion 130a extending inside a contact region 141 of the base region 140 and electrically connected to the base region 140.

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

Semiconductor devices include a semiconductor well layer having a first dopant polarity. A collector terminal is on a top surface of the semiconductor well layer, having a second dopant polarity. An emitter terminal is on the top surface of the semiconductor well layer, having the second dopant polarity. A conductor contacts a bottom surface of the semiconductor well layer and extends laterally below the collector terminal and the emitter terminal.

A semiconductor device includes a substrate; a fin structure disposed over the substrate; a gate structure disposed over the substrate, wherein an extension direction of the fin structure intersects an extension direction of the gate structure; and a first well disposed under the gate structure, corresponding to an emitter region of the semiconductor device, and having a first conductivity type, wherein the first well is adjacent to a well block layer, and the well block layer is disposed under the gate structure in the emitter region; wherein the well block layer has a first doping concentration of a well implant, the first well has a second doping concentration of the well implant, and the first doping concentration is less than the second doping concentration.

A bipolar junction transistor includes an emitter region, a base region, a collector region and a plurality of fin structures. The emitter region is disposed on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are disposed in the base region and surround the emitter region, and the plurality of fin structures fixedly extend along a direction and parallel to each other.

A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.

A bipolar junction transistor includes an emitter region, a base region, a collector region and an isolation structure. The base region is disposed adjacent to a first side of the emitter region. The collector region is disposed adjacent to a second side of the emitter region. The isolation structure is disposed between the emitter region and each of the base region and the collector region.

A semiconductor device includes a base region having a first conductivity type, the base region extending into a top surface of a semiconductor layer, a collector region having an opposite second conductivity type, the collector region extending from the top surface into the semiconductor layer and spaced apart from the base region, and an emitter region having the second conductivity type, the emitter region extending from the top surface into the base region and having first and second faces along a junction between the emitter region and the base region.