An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that is capable of reducing a base resistance and a turn-on voltage as compared to a conventional technique are provided. In an epitaxial wafer for a heterojunction bipolar transistor that includes a collector layer made of GaAs, a base layer (second base layer) formed on the collector layer and made of InGaAs, and an emitter layer formed on the second base layer and made of InGaP, a base layer (first base layer) made of GaAs is interposed between the collector layer and the second base layer.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.

A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.