One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.

A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.