Patent classifications
H10D10/01
Bipolar Transistor
A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers
Bidirectional bipolar transistors with two-surface cellular geometries
A two-surface bidirectional power bipolar transistor is constructed with a two-surface cellular layout. Each emitter/collector region (e.g. doped n-type) is a local center of the repeated pattern, and is surrounded by a trench with an insulated field plate, which is tied to the potential of the emitter/collector region. The outer (other) side of this field plate trench is preferably surrounded by a base connection region (e.g. p-type), which provides an ohmic connection to the substrate. The substrate itself serves as the transistor's base.
TRENCH-GATE TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
Superlattice lateral bipolar junction transistor
A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
ESD protection device
An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.
METHOD OF FORMING A BICMOS SEMICONDUCTOR CHIP THAT INCREASES THE BETAS OF THE BIPOLAR TRANSISTORS
The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.
FET—bipolar transistor combination
A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
FET - BIPOLAR TRANSISTOR COMBINATION
A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A bipolar junction transistor includes a first well region having a first conductive type, a second well region disposed adjacent to the first well region and having a second conductive type, a base disposed on the first well region and having the first conductive type, an emitter disposed on the first well region and having the second conductive type, and a collector disposed on the second well region and having the second conductive type. The first well region comprises a first impurity region and a second impurity region having an impurity concentration lower than that of the first impurity region. The base is disposed on the first impurity region, and the emitter is disposed on the second impurity region.
Bipolar transistor manufacturing method
A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.