A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed.

A low-damage etching method for a III-Nitride structure is disclosed. The method comprises: forming an etching mask on the III-Nitride structure, which is formed on a substrate; and etching the III-Nitride with the etching mask, wherein a temperature of the substrate changes dynamically or is kept at a constant temperature point between 200 C. and 700 C. during the etching.

A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.

A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape.

Provided is a semiconductor package including a Si substrate, a drift layer, a buffer layer, an anode electrode, a trench, a semiconductor apparatus, an anode terminal, a cathode terminal, and a sealing resin.

A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure.

A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.

A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of Al.sub.zGa.sub.1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of Al.sub.xGa.sub.1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of Al.sub.yGa.sub.1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

The occurrence of a short-channel effect is suppressed. A semiconductor device includes a semiconductor layer having an upper surface portion, a lower surface portion, and a side surface portion, and a field-effect transistor in which a channel forming portion is provided in the semiconductor layer. The field effect transistor includes a gate electrode provided in the channel forming portion of the semiconductor layer over the upper surface portion and the side surface portion of the semiconductor layer with a gate insulating film interposed therebetween, and a pair of main electrode regions provided on an outer side of the semiconductor layer in a channel length direction of the channel forming portion and separated from each other with the channel forming portion interposed therebetween. Each of the pair of main electrode regions includes a conductor layer that is provided in contact with the side surface portion of the semiconductor layer and that is in a layer different from the semiconductor layer.