A semiconductor device includes a chip that has a main surface, a gate resistor that includes a trench resistor structure formed in the main surface, a gate pad that has a lower resistance value than the trench resistor structure and is arranged on the main surface such as to be electrically connected to the trench resistor structure, and a gate wiring that has a lower resistance value than the trench resistor structure and is arranged on the main surface such as to be electrically connected to the gate pad via the trench resistor structure.

The semiconductor device includes a chip which has a first surface on one side and a second surface on the other side, a plurality of IGBT regions which are provided at an interval in the chip, a boundary region which is provided in a region between the plurality of IGBT regions in the chip, a first conductivity type cathode region which is formed in a surface layer portion of the second surface in the boundary region, and a second conductivity type well region which is formed in a surface layer portion of the first surface in the boundary region.

A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.

Provided is a semiconductor integrated circuit including a metal-oxide-semiconductor (MOS) switch, in which the MOS switch includes a first main MOS transistor having a first polarity, a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor, and a switch control circuit that supplies a first voltage according to a control signal to a gate of the first main MOS transistor, supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor, and is configured to be capable of adjusting a slew rate of each of the first voltage and the second voltage.

A monolithically integrated semiconductor device structure includes: a substrate and a transistor; the substrate includes a transistor region; the transistor is positioned above the transistor region comprising at least one first trench and at least one second trench that are arranged in a horizontal direction and extend in a vertical direction; and the first trench is disposed below a drain of the transistor, and the second trench is disposed below a non-drain region of the transistor. In the present disclosure, the first trench and the second trench that are disposed in the substrate of the monolithically integrated semiconductor device structure, which may reduce the equivalent dielectric constant of the substrate and improve the equivalent resistivity, so that the parasitic capacitance and leakage current of the substrate below the transistor are reduced.

A semiconductor device includes a semiconductor substrate. A well resistor is in the semiconductor substrate. A field plate is above the well resistor. An insulator is between the well resistor and the field plate. The well resistor includes a first terminal and a second terminal. The field plate may be coupled to the first terminal or the second terminal.

An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.