Drive substrates and display panels are provided. In a thin film transistor of the drive substrate, a structure with double-gate and double-active layer is formed by a first active layer, a first gate, a first sub-gate of a second gate, and a part of a second active layer in an area adjacent to an output electrode; and a structure with single active layer and top gate is formed by a second sub-gate of the second gate and a part of the second active layer in an area adjacent to an input electrode. The first gate and the second gate together control a first channel of the first active layer and a first portion of a second channel of the second active layer.

An array substrate includes a substrate, a semiconductor layer over the substrate, a gate over a side of the semiconductor layer away from the substrate, and a source and a drain on sides of the gate. The semiconductor layer includes a channel region, a first doping region, and a first ohmic contact region, which are sequentially connected. A shielding layer is between the substrate and the semiconductor layer. The shielding layer is connected to a fixed potential, and the shielding layer at least partially overlaps with the first doping region in a direction perpendicular to a plane of the substrate.

A display element includes a substrate, a three-colored LED light emitting structure, a first insulation layer, a first active device layer, at least one conductive via and at least one electrode. The three-colored LED light emitting structure is located on the substrate. The first insulation layer is located on the fourth semiconductor layer. The first active device layer is located on the first insulation layer, and the first active device layer includes at least one transistor. The conductive via extends from the first active device layer to and electrically connects at least one of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The electrode is located upon the first active device layer.

Related to the field of display panels, an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: the base substrate, the buffer layer, the active layer, the gate insulation layer, the gate, the interlayer insulation layer, the source, and the drain, which are stacked together. By using the gate insulation layer as a conductive mask of the active layer, and by adjusting the width of the gate and the width of the gate insulation layer, a width difference between the channel region and the gate is within the preset range, which reduces the problem of excessive width difference caused by the diffusion phenomenon of the channel region, and can at the same time meet the switching characteristics requirements of the thin film transistor and the definition requirements of the display panel.

Provided is an electro-optical device including a transistor, a pixel electrode provided on a light incidence side of the transistor, a lens layer provided in a layer between the transistor and the pixel electrode, and a relay layer serving as a first relay layer that is provided in a layer between the lens layer and the pixel electrode and electrically connected to the pixel electrode, wherein the relay layer includes WSi on the pixel electrode side.

A display apparatus may include a substrate; a plurality of pixels on the substrate in a row direction and a column direction and including a plurality of sub-pixels; a plurality of sub-pixel circuits in the plurality sub-pixels on the substrate; and a plurality of gate lines on the substrate and connected to the plurality of sub-pixel circuits. Each of the plurality of sub-pixels may include a plurality of sub-light emitting diodes configured to emit light of the same color, at least one sub-light emitting diode of one sub-pixel included in one of the plurality of pixels may be configured to be driven by a gate line, and a sub-light emitting diode of another sub-pixel included in the same one of the plurality of pixels may be configured to be driven by another gate line that is different from the gate line.

A method for fabricating a single pixel micro LED device for a display panel includes providing a substrate having a pixel driver and fabricating an LED structure layer stacked on top of the substrate. The method further includes bonding the substrate and the LED structure layer together by a bonding layer. The LED structure layer is electrically connected to the pixel driver via the bonding layer. In some embodiments, before bonding the substrate and the LED structure layer, the method includes coating a reflection layer on the LED structure layer. In some embodiments, the method includes patterning the LED structure layer to form a red light LED.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.