Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

A display panel and a display device. Because the pixel distribution density in a second display subarea (A12) is lower than that in a first display subarea (A11), the quantities of sub-pixels (pix) connected to scanning lines are not completely the same; a sub-pixel row having the greatest quantity of sub-pixels (pix) in the display panel is taken as a reference sub-pixel row, the quantity of the sub-pixels (pix) of the reference sub-pixel row is taken as a reference value, a sub-pixel row having the quantity of sub-pixels (pix) smaller than the reference value is taken as a compensation sub-pixel row, and a scanning line connected to the compensation sub-pixel row is taken as a first scanning line; the display panel is provided with load compensation units corresponding to at least part of the first scanning lines, and the load compensation units are located in the second display subarea.

A method of fabricating an array substrate is provided. The array substrate includes a display region and a non-display region. The array substrate further includes a substrate, a first transparent layer disposed on the substrate corresponding to the display region, an interlayer insulating layer disposed on the substrate, and a second transparent layer disposed on the interlayer insulating layer.

It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like.

Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.

An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 510.sup.19 atoms/cm.sup.3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Provided are display panels and display apparatus. The display panel includes a driving array layer including a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit. The pixel circuit includes first and third transistors. The driving circuit includes second and fourth transistors. The first to fourth transistors include an active layer including silicon, an active layer including oxide semiconductor, an active layer including oxide semiconductor, and an active layer including silicon. The first and the third transistors are switching transistors of the pixel circuit, |W1/L1-W4/L4|<|W2/L2-W3/L3|; or the first and the third transistors are a driving transistor and a switching transistor of the pixel circuit, respectively, |W1/L1-W4/L4|>5*|W2/L2-W3/L3|; or the first and third transistors are a switching transistor and a driving transistor of the pixel circuit, respectively, 5*|W1/L1-W4/L4|<|W2/L2-W3/L3|.