Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

Disclosed herein is a semiconductor device including first and second capacitor structures formed to be spaced apart from each other on a semiconductor substrate, wherein the first capacitor structure includes a first trench formed in the semiconductor substrate, first, second, and third electrode layers disposed in the first trench, and first, second, and third dielectric layers disposed in an interlaced structure with the semiconductor substrate and the first to third electrode layers, the second capacitor structure includes a second trench formed in the semiconductor substrate, fourth, fifth, and sixth electrode layers disposed in the first trench, and fourth, fifth, and sixth dielectric layers disposed in an interlaced structure with the semiconductor substrate and the fourth to sixth electrode layers, and a connection blocking area formed between the first and second capacitor structures to block connections between elements constituting the first capacitor structure and elements constituting the second capacitor structure.

A capacitor structure and a forming method thereof are provided. The capacitor structure includes a substrate and a bottom electrode composite layer on the substrate. The bottom electrode composite layer includes a first electrode layer and a second electrode layer on the first electrode layer. An oxidation rate of a material of the second electrode layer is lower than an oxidation rate of a material of the first electrode layer. The capacitor structure also includes a dielectric structure layer on the bottom electrode composite layer.

A semiconductor device includes a metal-oxide-metal (MOM) cell including a first bus at a first elevation and extending along a first direction, and a second bus at a second elevation, extending along a second direction different from the first direction, and electrically connected to the first bus through a via. The MOM cell also includes a first group of fingers at the first elevation and extending along the first direction; and a second group of fingers at the second elevation and extending along the second direction. Each finger of the first group of fingers is electrically connected to the second bus through a corresponding via, each finger of the second group of fingers is electrically connected to the first bus through a corresponding via, and each finger of the first group of fingers overlaps each finger of the second group of fingers.

A semiconductor device includes a metal-insulator-metal capacitor disposed between a first metallization level and a second metallization level, the metal-insulator-metal capacitor comprising a first electrode, a second electrode and a third electrode. A first via is extended from and contacts a conductive line of the second metallization level, and a second via is extended from and contacts the first via. The second via contacts the first electrode and the third electrode of the metal-insulator-metal capacitor. A slope of a side surface of the first via is different from a slope of a side surface of the second via.

A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.

The application relates to an electrode layer, a capacitor and methods for electrode layer and capacitor manufacture. The method for electrode layer manufacture comprises the following steps: forming a first electrode layer, the first electrode layer comprising a doped Titanium Nitride (TiN) layer; and forming a second electrode layer on the surface of the first electrode layer, the second electrode layer comprising a TiN layer or a work function layer.

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.