A lower electrode is made of a TiN-based material and provided at a base of a dielectric film in a DRAM capacitor. The lower electrode includes first TiON films provided at opposite outer sides, the first TiON films having a relatively low oxygen concentration, and a second TiON film provided between the first TiON films, the second TiON film having a relatively high oxygen concentration.

A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.

A manufacturing method for a micromechanical sensor device and a corresponding micromechanical sensor device. The method includes providing a substrate including at least one first through a fourth parallel trenches; depositing a layer onto the front side, the trenches being sealed, and structuring the layer, contact structures being formed in the layer above the second and fourth trenches; oxidizing of outwardly free-standing side surfaces of the contact structures as well as of the second and fourth trenches, at least in areas; depositing and structuring a first metallic contacting material, the contact structures being filled with the first metallic contacting material, at least in areas; opening the second trench and the fourth trench; galvanic deposition of a second metallic contacting material into the second and fourth trenches, resulting in the formation of a pressure-sensitive capacitive capacitor structure; and opening the first trench from the front side of the substrate.

Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.

The EL substrate includes semiconductor layers of TFTs, a pixel electrode, and an upper part electrode of a Cs section which are provided on a gate insulating film. The semiconductor layers are covered with a protective film which has openings via which the pixel electrode and the upper part electrode are exposed. The semiconductor layers are an oxide semiconductor layer, and the pixel electrode and the upper part electrode are reduction electrodes of the oxide semiconductor layer.

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a free layer comprising CoFeGeB alloy, and having a changeable magnetization direction that is perpendicular to the free layer; a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and a bottom layer positioned under the free layer, and having a B2 structure to improve a perpendicular magnetic crystalline anisotropy of the free layer.