To provide a thin film capacitor having a large capacitance. A thin film capacitor includes a metal foil having roughened main surfaces, a dielectric film covering the main surfaces, an electrode layer contacting the metal foil through an opening formed in the dielectric film and having a surface formed as a metal terminal, an electrode layer contacting the dielectric film without contacting the metal foil and having a surface formed as a metal terminal, and an electrode layer contacting the dielectric film without contacting the metal foil. The electrode layers include a conductive polymer layer contacting the dielectric film.

A MIM capacitor including a bottom metal layer on a substrate, a first contact window in the bottom metal layer; and a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, where the first dielectric spacer has a rounded upper surface, where a bottom most surface of the bottom metal layer is substantially flush with a bottom most surface of the first insulator layer. A method including forming a bottom metal layer on a substrate, forming a first contact window in the bottom metal layer, and forming a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, wherein the first dielectric spacer has a rounded upper surface.

To provide a thin film capacitor having high adhesion with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. An angle a formed by the other main surface of the metal foil and a side surface thereof is more than 20 and less than 80. The side surface is thus tapered at an angle of more than 20 and less than 80, so that it is possible to suppress warpage and to enhance adhesion with respect to a multilayer substrate when the thin film capacitor is embedded in the multilayer substrate.

A method for forming a semiconductor memory structure includes forming a bottom electrode layer over an active region, depositing a first high-k dielectric material on the bottom electrode layer, depositing a second high-k dielectric material on the first high-k dielectric material, annealing the first and second high-k dielectric materials, after the annealing process, depositing a third high-k dielectric material on the second high-k dielectric material, and forming a top electrode layer on the third high-k dielectric material.

A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

A method of fabricating a semiconductor device, including forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.

Provided is a semiconductor device including a metal film which can be formed with lower costs but still manage to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed on the insulating film. The metal film includes a stacked structure of: a first metal film disposed on the insulating film to directly contact the insulating film; a second metal film disposed on the first metal film to directly contact the first metal film; and the first metal film disposed on the second metal film to directly contact the second metal film, the second metal film having a work function greater than 4.8 eV and being different from the first metal film in material, wherein an oxidation resistance of the first metal film is greater than that of the second metal film.