In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.

An approach to forming a semiconductor structure with improved negative bias temperature instability includes diffusing fluorine atoms into a semiconductor structure by an anneal in a fluorine containing gas. The approach includes removing a pFET work function metal layer from an area above an nFET wherein the area above the nFET includes at least the area over the nFET. Additionally, the approach includes depositing a layer of nFET work function metal on a remaining portion of the pFET work function metal and depositing a gate metal over the nFET work function metal layer. Furthermore, the method includes performing an anneal in a reducing environment followed by a high temperature anneal.

A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity.

A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer includes a first gate metal layer formed along both sides of the lower portion of the fin structure, the first gate metal layer having a first workfunction, and a second gate metal layer formed disposed over the first gate metal layer and wrapped around the upper portion of the fin structure, the second gate metal layer having a second workfunction. The first and the second workfunctions are different.

A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Disclosed is a display device including a seal material and a sealing material. The seal material surrounds a pixel portion and the sealing material overlaps with at least any of a driver circuit and a protective circuit. The pixel portion includes a planarization layer and an organic resin film each having an opening, an end portion of which is rounded. The pixel portion further includes a first electrode, a light-emitting member over the first electrode, and a second electrode over the light-emitting member. Part of the first electrode and part of the organic resin film are located in the opening of the planarization layer. Part of the light-emitting member and Part of the second electrode are located in the opening of the organic resin film.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.