A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.

A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide includes a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material that includes the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. An interface between a dummy gate and a gate dielectric layer of a gate-last transistor structure may be similarly formed.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.

A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.