A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.

A semiconductor memory device includes pairs of metal lines and memory arrays. Each of the memory arrays includes first and second sets of thin film transistors (TFTs), a first switch transistor, and a second switch transistor. The TFTs in the first and second sets are electrically connected to each other in parallel. The first switch transistor is electrically connected in series to one of the TFTs in the first set and one of the metal lines in a corresponding one of the pairs of the metal lines. The second switch transistor is electrically connected in series to one of the TFTs in the second set and the other one of the metal lines in the corresponding one of the pairs of the metal lines.

A ferroelectric random access memory (FeRAM) cell may include an oxide insertion layer between the electron barrier layer and the metal glue layer of the source/drain regions of the FeRAM cell. The oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent dissociation and/or out-diffusion of the electron barrier layer at high processing temperatures. Thus, the oxide insertion layer may enable the metal glue layer to be formed over the electron barrier layer with low surface roughness, which may enable increased adhesion between the metal glue layer and the source/drain electrodes of the source/drain regions. In this way, the oxide insertion layer may enable low electrical resistance to be achieved for the FeRAM cell and/or may reduce the likelihood of failures in the FeRAM cell, among other examples.

A vertical semiconductor device includes: a plurality of insulation patterns on a substrate, the plurality of insulation patterns being spaced apart from each other in a vertical direction; a plurality of channel structures being spaced apart from each other in a first direction, each of the plurality of channel structures including interface insulation patterns, and the plurality of channel structures disposed in a first trench extending in the first direction and passing through the insulation patterns in the vertical direction; a ferroelectric structure on an outer surface of each of the plurality channel structures, the ferroelectric structure protruding in a direction toward a gap between some of the insulation patterns in the vertical direction; and a conductive pattern on a sidewall of the ferroelectric structure, the conductive pattern filling the gap in the vertical direction.

A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO.sub.2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.