Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile).

A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device. The structure comprises a first electrode including a first doped region in a semiconductor layer and a second doped region in the semiconductor layer, an interconnection that is configured to connect the first doped region to the second doped region, a ferroelectric layer on the semiconductor layer, and a second electrode including a first section and a second section on the ferroelectric layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material.

A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 . Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

It is an object to provide a ferroelectric thin film having much higher ferroelectric properties than conventional Sc-doped ferroelectric thin film constituted by aluminum nitride and also having stability when applied to practical use, and also to provide an electronic device using the same. There are provided a ferroelectric thin film represented by a chemical formula M1.sub.1-XM2.sub.XN, wherein M1 is at least one element selected from Al and Ga, M2 is at least one element selected from Mg, Sc, Yb, and Nb, and X is within a range of 0 or more and 1 or less, and also an electronic device using the same.

Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.