A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.

A power supply module includes a first substrate; a control IC, a capacitor, a first electronic component, a second electronic component, a third electronic component and a fourth electronic component on a principal surface of the first substrate; a first submodule including a second substrate above the first electronic component, the second electronic component, the third electronic component, and the fourth electronic component and including a fifth electronic component, a sixth electronic component, and a seventh electronic component on a principal surface of the second substrate; and a resin covering an upper portion of the first submodule.

[Theme] To provide a chip capacitor capable of easily and rapidly accommodating a plurality of types of capacitance values using a common design and a method for manufacturing the chip capacitor. [Solution] A chip capacitor 1 includes a substrate 2, a first external electrode 3, a second external electrode 4, capacitor elements C1 to C19, and fuses F1 to F9 disposed on the substrate 2. The capacitor elements C1 to C19 respectively include a first electrode film 11, a first capacitance film 12 on the first electrode film 11, a second electrode film 13 disposed on the first capacitance film 12 and facing the first electrode film 11, a second capacitance film 17 on the second electrode film 13, and a third electrode film 16 disposed on the second capacitance film 17 and facing the second electrode film 13 and are connected between the first external electrode 3 and the second external electrode 4. The fuses F1 to F9 are each interposed between the capacitor elements C1 to C19 and the first external electrode 3 or the second external electrode 4 and are capable of disconnecting each of the capacitor elements C1 to C19.

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.

Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.

This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins.

A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.