A semiconductor device is provided. The Semiconductor device includes a first active fin and a second active fin disposed on a substrate. A first gate electrode intersects the first active fin. A second gate electrode intersects the second active fin. A first gate insulation layer includes a first high dielectric constant insulation layer. The first gate insulation layer is disposed between the first gate electrode and the first active fin. A second gate insulation layer includes a second high dielectric constant insulation layer. The second gate insulation layer is disposed between the second gate electrode and the second active fin. A thickness of the first high dielectric constant insulation layer is thicker than a thickness of the second high dielectric constant insulation layer.

A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.

A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material.

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.

After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is intentionally etched and undercut regions that are formed are filled and pinched off with a dielectric material of a conformal dielectric liner. Portions of the conformal dielectric liner in the undercut regions are not subject to the undercut during an epitaxial pre-clean process performed prior to forming an epitaxial source region and an epitaxial drain region on opposite sides of the sacrificial gate structure and remain in the undercut regions after forming the epitaxial source region and the epitaxial drain region.

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.