A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

A semiconductor device may include a semiconductor fin, a source/drain region extending from the semiconductor fin, and a gate electrode over the semiconductor fin. The semiconductor fin may include a first well and a channel region over the first well. The first well may have a first dopant at a first dopant concentration and the channel region may have the first dopant at a second dopant concentration smaller than the first dopant concentration. The first dopant concentration may be in range from 10.sup.17 atoms/cm.sup.3 to 10.sup.19 atoms/cm.sup.3.

In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate.

An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.

A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.