In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

An integrated circuit product including a first layer of insulating material that includes a first insulating material, a metallization blocking structure positioned in an opening in the first layer of insulating material, a second layer of insulating material including a second insulating material positioned below the metallization blocking structure, a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure, and a conductive metallization line positioned in the metallization trench on opposite sides of the metallization blocking structure.

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.