A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

Ferroelectric materials and more particularly cerium-doped ferroelectric materials and related devices and methods are disclosed. Aspects of the present disclosure relate to ferroelectric layers of hafnium-zirconium-oxide (HZO) doped with cerium that enable reliable ferroelectric fabrication processes and related structures with significantly improved cycling endurance performance. Such doping in ferroelectric layers also provides the capability to modulate polarization to achieve a desired operation voltage range. Doping concentrations of cerium in HZO films are disclosed with ranges that provide a stabilized polar orthorhombic phase in resulting films, thereby promoting ferroelectric capabilities. Exemplary fabrication techniques for doping cerium in HZO films as well as exemplary device structures including metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) structures are also disclosed.

A power transistor is formed by a plurality of transistor cells electrically connected in parallel. Each transistor cell includes a gate structure including a gate electrode coupled to a control terminal and a gate dielectric stack, the gate dielectric stack including a ferroelectric insulator. A method of operating the power transistor includes: switching the power transistor in a normal operating mode by applying a switching control signal to the control terminal, the switching control signal having a maximum voltage and a minimum voltage; and setting the ferroelectric insulator into a defined polarization state by applying a first voltage pulse to the control terminal, the first voltage pulse exceeding the maximum voltage of the switching control signal.

The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.

The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.