The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.

The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.

A semiconductor memory device may include a pillar, a gate and at least one ferroelectric layer. The pillar may include a source, a drain and a channel region. The drain may be arranged over the source. The channel region may be arranged between the source and the drain. The gate may be formed on an outer surface of the pillar. The ferroelectric layer may be interposed between the pillar and the gate.

An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 110.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (C.sub.FE) is matched to the sum of the gate capacitance (C.sub.MOS) and the gate edge capacitance (C.sub.EDGE), wherein the gate edge capacitance (C.sub.EDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

A device includes a substrate, a semiconductor layer and a ferroelectric layer. The semiconductor layer is over the substrate. The semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. The ferroelectric layer is over the semiconductor layer. The ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.

A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200 C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.