A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

Disclosed is a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.

A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high- metal oxide layer on the interfacial layer, the high- metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high- metal oxide capping layer on the high- metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high- metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high- metal oxide layer to form a dipole region.

The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other, a source/drain pattern electrically connected to the plurality of semiconductor patterns, an inner gate electrode between adjacent first and second semiconductor patterns of the plurality of semiconductor patterns, an inner gate insulating layer between the inner gate electrode and the first and second semiconductor patterns, an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer, and an inner spacer between the inner gate insulating layer and the source/drain pattern. As the inner gate insulating layer includes an inner gate spacer, the inner gate electrode may stably fill the inner gate space. As a result, the electrical characteristics of the semiconductor device may be improved.

A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

Provided is a ferroelectric field effect transistor including a source region, a drain region, a channel provided between the source region and the drain region, a ferroelectric layer provided on the channel and including a ferroelectric material including an oxide of a first element, a gate-interposed layer provided on the ferroelectric layer and including a paraelectric material including an oxide of a second element different from the first element, and a gate electrode provided on the gate-interposed layer, wherein the gate-interposed layer includes a first interposed layer adjacent to the ferroelectric layer, and a second interposed layer adjacent to the gate electrode, the first interposed layer includes a mixture of the first element and the second element, and a ratio of the first element in the first interposed layer may be greater than a ratio of the first element in the ferroelectric layer.

Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.