Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a first gate dielectric layer and floating gate layer; forming a mask layer as a spacer on a sidewall of a remaining portion of the second shielding layer, and patterning the floating gate layer with the mask layer as a mask, and then removing the mask layer; and forming a second gate dielectric layer, and forming a gate conductor as a spacer on the sidewall of the remaining portion of the second shielding layer.

An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function .sub.MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or flare the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function .sub.MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Provided is a semiconductor device including: a substrate containing a semiconductor material; an electrode provided on a substrate surface of the substrate, the electrode containing a metal material; and a mixed member provided on the substrate surface to be in contact with the electrode, the mixed member containing the semiconductor material and the metal material, in which a portion of the substrate surface is exposed at an end of the substrate.

The present disclosure relates to semiconductor structures and, more particularly, to under-body source contact structures and methods of manufacture. The structure includes: a gate structure on a semiconductor layer; a drift region within the semiconductor layer, below the gate structure; a body region within the semiconductor layer, below the gate structure; a contact region within the body region, the contact region being devoid of a silicide contact; and a silicide contact remote from the contact region within the semiconductor layer.

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

This application is directed to integrating metal oxide semiconductor (MOS) transistors and Schottky barrier diodes (SBDs). An integrated planar semiconductor device includes a substrate, an SBD joining an SBD semiconductor and a barrier metal on the substrate, and a MOS transistor formed on the substrate and including a gate, a source, and a drain. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and is in contact with the SBD semiconductor. In some implementations, the drain of the MOS transistor includes an extended drain structure. The SBD semiconductor includes a first semiconductor portion and a second semiconductor portion. A doping profile of the extended drain structure is substantially the same as that of the second semiconductor portion. A doping concentration of a channel region of the MOS transistor is substantially the same as that of the first semiconductor portion.