A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of In.sub.xGa.sub.1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs.sub.1-yN.sub.y with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Methods to form multi V.sub.t channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.

Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.