A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.

N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers on opposite sides of the first channel layer; forming second source/drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. The semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. The semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. The dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. The semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. The gate structure is divided into two portions by the cutting structure.

An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.

A semiconductor device comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between first and second semiconductor patterns among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source/drain pattern, wherein the inner gate spacer includes a center portion and an edge portion, the center portion has a first thickness in a second direction, the edge portion has a second thickness in the second direction, the first thickness is greater than the second thickness, the first and second semiconductor patterns are adjacent to each other in a third direction.

An exemplary device includes a frontside power rail disposed over a frontside of a substrate, a backside power rail disposed over a backside of the substrate, an epitaxial source/drain structure disposed between the frontside power rail and the backside power rail. The epitaxial source/drain structure is connected to the frontside power rail by a frontside source/drain contact. The epitaxial source/drain structure is connected to the backside power rail by a backside source/drain via. The backside source/drain via is disposed in a substrate, and a dielectric layer is disposed between the substrate and the backside power rail. The backside source/drain via extends through the dielectric layer and the substrate. A frontside silicide layer may be between the frontside source/drain contact and the epitaxial source/drain structure, and a backside silicide layer may be between the backside source/drain contact and the epitaxial source/drain structure, such that the epitaxial source/drain structure between silicide layers.

A semiconductor device includes an active pattern including a lower pattern extending a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, the plurality of sheet patterns including an uppermost sheet pattern, a plurality of gate structures disposed to be spaced apart from each other in the first direction on the active pattern and including gate electrodes extending in a third direction and gate spacers on sidewalls of the gate electrodes and a source/drain pattern disposed between the gate structures adjacent to each other and including a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, wherein the semiconductor liner film covers a portion of an upper surface of an uppermost sheet pattern.