A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing.

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode.

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (NCEM). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (DOEs), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.

An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer.

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.