A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1.sup.stsource/drain region connected to a 1.sup.st channel structure; and a 2.sup.nd source/drain region, above the 1.sup.st source/drain region, connected to a 2.sup.nd channel structure above the 1.sup.st channel structure, wherein the 2.sup.nd channel structure has a smaller length than the 1.sup.st channel structure in a channel-length direction, in which the 2.sup.nd source/drain region is connected to a 3.sup.rd source/drain region through the 2.sup.nd channel structure.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

Provided is a semiconductor device which includes: a 1.sup.st source/drain region connected to a 1.sup.st channel structure which is controlled by a 1.sup.st gate structure; a 2.sup.nd source/drain region, above the 1.sup.st source/drain region, connected to a 2.sup.nd channel structure which is controlled by a 2.sup.nd gate structure; and a middle isolation structure between the 1.sup.st gate structure and the 2.sup.nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.

A semiconductor device includes a first active pattern extending in a first direction, a second active pattern on the first active pattern and extending in the first direction, a gate structure on the first active pattern and the second active pattern and extending in a second direction intersecting the first direction, a first source/drain region on side faces of the gate structure and connected to the first active pattern, a second source/drain region on the side faces of the gate structure and connected to the second active pattern, and an intermediate connecting layer which includes a first intermediate conductive pattern between the first active pattern and the second active pattern, and a second intermediate conductive pattern connected to the first intermediate conductive pattern between the first source/drain region and the second source/drain region.

A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.