A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with high reliability is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order over the first insulating layer. The semiconductor layer contains indium and oxygen and has a composition falling within a range obtained by connecting first coordinates (1:0:0), second coordinates (2:1:0), third coordinates (14:7:1), fourth coordinates (7:2:2), fifth coordinates (14:4:21), sixth coordinates (2:0:3), and the first coordinates in this order with a straight line in a ternary diagram showing atomic ratios of indium to an element M and zinc. In addition, the element M is one or more of gallium, aluminum, yttrium, and tin.

A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.

Various forms of Mg.sub.xGe.sub.1xO.sub.2x are disclosed, where an epitaxial layer comprises single crystal Mg.sub.xGe.sub.1xO.sub.2x, with x having a value of 0x<1, wherein the single crystal Mg.sub.xGe.sub.1xO.sub.2x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal Mg.sub.xGe.sub.1xO.sub.2x is grown. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1xO.sub.2x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

A crystalline oxide thin film contains an In element, a Ga element and an Ln element, in which the In element is a main component, the Ln element is at least one element selected from the group consisting of La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and an average crystal grain size D.sub.1 is in a range from 0.05 m to 0.5 m.

A crystalline oxide thin film contains an In element, a Ga element and an Ln element, in which the In element is a main component, the Ln element is at least one element selected from the group consisting of La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and an average crystal grain size D.sub.1 is in a range from 0.05 m to 0.5 m.

In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.