A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.

A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.

An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.

A semiconductor structure includes a first magnetic layer, an insulative oxide layer, an oxygen trapping layer and a cap layer. The insulative oxide layer is over the first magnetic layer. The oxygen trapping layer is over the insulative oxide layer. The oxygen concentration of the oxygen trapping layer is less than an oxygen concentration of the insulative oxide layer. The cap layer is over the oxygen trapping layer.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

A three-dimensional production method for a functional element structure body according to the invention is a three-dimensional production method for a functional element structure body, which includes an electrical functional element section having a terminal and an insulating member provided on the periphery of the functional element section in a state where at least the terminal is exposed to the outside, and includes a layer formation step of forming one layer in a layer forming region by supplying a first flowable composition containing first particles for the functional element section from a first supply section, and supplying a second flowable composition containing second particles for the insulating member from a second supply section, a shaping step of shaping the functional element structure body by repeating the layer formation step, and a solidification step of performing solidification by applying energy to the first particles and the second particles in the layer.

A method for providing an inductively loaded integrated circuit includes providing a wafer with an integrated circuit formed thereon, the integrated circuit comprising at least one substrate via, including one or more substrate vias that are to be inductively loaded, and fabricating an inductive element on the backside of the wafer that electrically connects to the substrate vias that are to be inductively loaded. A corresponding apparatus includes a wafer with an integrated circuit formed on a top side of the wafer and an inductive element formed on a back side of the wafer, and at least one substrate via that extends through the wafer and electrically connects the inductive element to the integrated circuit. In certain embodiments, the inductive element comprises a plurality of conductive layers. In some embodiments, the inductive element comprises multiple turns on each conductive layer.

A semiconductor device includes a first unit, a second unit, and a third unit placed on the first unit and on the second unit. The first unit includes a first semiconductor substrate, a first element insulating layer, and a first insulation element. The second unit includes a second semiconductor substrate, a second element insulating layer, and a second insulation element. The third unit includes a third semiconductor substrate, a third element insulating layer, a third insulation element, and a fourth insulation element. In a unit arrangement state, the first insulation element and the third insulation element are placed to face each other in the Z-direction, and the second insulation element and the fourth insulation element are placed to face each other in the Z-direction.