A semiconductor structure may include a substrate having a surface, an isolation structure formed on the surface, an active region formed on the surface adjacent to the isolation structure, a gate extended over the isolation structure and the active region, and a source region formed within the active region. The source region may include a first subregion formed adjacent to a first portion of the gate and the isolation structure, the first subregion having a first doping and a second subregion formed adjacent to a second portion of the gate, wherein the second subregion has a second doping different from the first doping.

A semiconductor device includes a first electrode, a semiconductor part located on the first electrode, an insulating member located in the semiconductor part, a first insulating film located on a portion of the semiconductor part, a second insulating film located on another portion of the semiconductor part, a second electrode located in the insulating member, a first wiring part connected to the second electrode, and a third electrode located on the semiconductor part, on the insulating member, and on the first insulating film. The second insulating film is thicker than the first insulating film. The first wiring part is located on the insulating member and on the second insulating film but not on the first insulating film.

A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The bidirectional diode unit may be arranged between the anode pad and the cathode pad on the front surface.

Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.

Provided is a semiconductor device that includes a drift region that is of a first conductivity type and is provided in a semiconductor substrate; a base region that is of a second conductivity type and is provided above the drift region; an accumulation region that is of the first conductivity type provided between the base region and the drift region; and an electric field relaxation region that is provided between the base region and the accumulation region, wherein the boundary between the electric field relaxation region and the accumulation region is a location for a half-value for the peak of the doping concentration of the accumulation region, and an integrated concentration of the electric field relaxation region is greater than or equal to 5E14 cm.sup.2 and less than or equal to 5E15 cm.sup.2.

A vertical field effect transistor, including a drift region having a first conductivity type, a trench structure on or above the drift region, a shielding structure, and a source/drain electrode. The trench structure includes at least one side wall at which a field effect transistor (FET) channel region is formed. The FET channel region includes a III-V heterostructure for forming a two-dimensional electron gas at a boundary surface of the III-V heterostructure. The shielding structure is situated laterally adjacent to the at least one side wall of the trench structure and extends vertically into the drift region or vertically further in the direction of the drift region than the trench structure. The shielding structure has a second conductivity type that differs from the first conductivity type. The source/drain electrode is electroconductively connected to the III-V heterostructure of the trench structure and to the shielding structure.

Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a plurality of vertical transistors, each comprising: a semiconductor layer having a leakage value lower than a pico-ampere and comprising a vertical semiconductor portion and at least one lateral semiconductor portion, a gate dielectric layer comprising a vertical gate dielectric portion on the vertical semiconductor portion and extending in the vertical direction, a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer. The disclosed semiconductor device further comprises a plurality of capacitors each coupled with the semiconductor layer of a corresponding one of the plurality of vertical transistors.

A silicon carbide semiconductor device includes an n-type drift region, a p-type body region, an n-type source region, a p-type contact region, a gate trench extending in a first direction, a gate insulating film, a gate electrode, a source electrode, an interlayer insulating film, a p-type electric field mitigation region, and a p-type connection region connecting the contact region and the electric field mitigation region. The electric field mitigation region includes a first region having a first dimension in a second direction perpendicular to the first direction, and a second region connected to the first region in the first direction and having a second dimension in the second direction smaller than the first dimension. The contact region includes a third region exposed via a contact hole provided in the interlayer insulating film and connected to the source electrode.

A high-electron mobility transistor includes a semiconductor body including a barrier region, a channel region, and a two-dimensional charge carrier gas channel, first and second electrodes that are each in electrical contact with the two-dimensional charge carrier gas channel, and a gate structure laterally in between the first and second electrodes, wherein the gate structure comprises a gate electrode and a first region of doped type III-V semiconductor material in between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of doped type III-V semiconductor material comprises a plurality of side faces that define a plan view geometry of the first region, and wherein in the plan view geometry of the first region at least two lateral boundaries of the first region that intersect one another extend along crystallographically equivalent planes of the doped type III-V semiconductor material.

An extension part of a lower electrode extending to an outer side of an upper electrode in the lower electrode further extends to an upper surface of a semiconductor substrate to cover an end portion of the upper electrode in an outer surrounding part of a trench located, in an outer surrounding region in an extension direction, and a width of the trench is smallest in a trench end portion.