Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1.sub.CONTACT over a bottom portion having a width W2.sub.CONTACT, wherein W2.sub.CONTACT<W1.sub.CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2.sub.CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (BTBT) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

A method of fabricating a semiconductor device includes providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.

A semiconductor structure is provided. A logic cell includes first and second nanostructure transistors. The first nanostructure transistor is formed in a first active region over a first well region having a first conductivity type. The second nanostructure transistor is formed in a second active region over a second well region having a second conductivity type. The first and second nanostructure transistors share a gate structure. First and second source/drain features of the first nanostructure transistor are formed in the first active region. Third and fourth source/drain features of the second nanostructure transistor are formed in a first portion and a second portion of the second active region, respectively. A first distance between the first active region and the first portion of the second active region is different from a second distance between the first active region and the second portion of the second active region.

A semiconductor device includes an active region that extends on the substrate in a first direction; a plurality of semiconductor layers disposed on the active region and that are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure disposed on the substrate and that crosses the active region and the plurality of semiconductor layers, surrounds each of the plurality of semiconductor layers, and extends in a second direction; a source/drain region disposed on at least one side of the gate structure and in contact with a portion of the plurality of semiconductor layers; and an epitaxial layer that is spaced apart from an uppermost semiconductor layer, is disposed below the source/drain region and between the active region and the source/drain region, and is in contact with at least a portion of the side surfaces of the lowermost semiconductor layer.

A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.

A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.