Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.

A method for manufacturing a semiconductor structure includes: forming a channel portion on a fin portion; forming two source/drain portions on the fin portion and at two opposite sides of the channel portion, in which each of the two source/drain portions includes a first semiconductor material that is doped with dopant impurities; and forming two bottom portions each of which is disposed between the fin portion and a corresponding one of the two source/drain portions, in which each of the two bottom portions includes a second semiconductor material that is different from the first semiconductor material and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the fin portion.

A semiconductor device manufacturing method includes the following steps. A well implant process is performed on a region of a substrate. A source/drain implant process is performed on the region of the substrate. An active area is defined on the region of the substrate. Shallow trench isolations are formed in the active area. An annealing process is performed to the region of the substrate.

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (BTBT) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.