Disclosed are a manufacturing method of a dual gate TFT substrate and a structure thereof. The manufacturing method of a dual gate TFT substrate includes sequentially manufacturing a bottom gate, a first isolation layer, an island shaped semiconductor layer, and a second isolation layer on a substrate; then, depositing a second metal layer, and implementing a patterning process to the second metal layer with one mask to form a source, a drain and a top gate at the same time; and then, sequentially manufacturing a third isolation layer and a pixel electrode. It can promote the stability of the TFT, reduce the amount of the masks, and shorten the process flow, simplifying the manufacture process and diminishing the production cost. In the structure of the dual gate TFT substrate, the structure is simple, and the stability of the TFT is better, and easy to manufacture.

The disclosure provides a display panel and a preparation method thereof. The display panel includes an array substrate and an opposite substrate. The array substrate includes a first substrate, a common electrode layer, a first metal layer, a second substrate, and a light-shielding layer. The common electrode layer includes a common electrode, a first electrode, and a groove, and the groove is disposed between the common electrode and the first electrode. The light-shielding layer includes a light-shielding part, and an orthographic projection of the light-shielding part on the first substrate covers an orthographic projection of the first electrode on the first substrate, an orthographic projection of the second electrode on the first substrate, and an orthographic projection of the groove on the first substrate.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first transistor, a first insulator over the first transistor, a second transistor over the first insulator, a second insulator over the second transistor, and a capacitor over the second insulator. The first insulator has a barrier property against oxygen and hydrogen. The second transistor includes an oxide semiconductor. The second insulator includes an oxygen-excess region. The capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The dielectric includes a third insulator having a barrier property against oxygen and hydrogen. The first insulator and the third insulator are in contact with each other on an outer edge of a region where the second transistor is located so that the second transistor and the second insulator are enclosed by the first insulator and the third insulator.

A display device includes a display element, a transistor configured to drive the display element, the transistor including a channel region, and a retention capacitor. An oxide semiconductor film is provided in areas across the transistor and the retention capacitor, the oxide semiconductor film including a first region formed in the channel region of the transistor, and a second region having a lower resistance than that of the first region. The second region is formed in the areas of the transistor and retention capacitor other than in the channel region.

An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.

A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.

A liquid crystal display device includes a gate line and a data line disposed on a substrate; a thin film transistor (TFT) provided between the gate line and the data line; a pixel electrode positioned on the entire surface of a pixel region of the substrate; an insulating layer positioned on the entire surface of the substrate and exposing the TFT and the pixel electrode; a pixel electrode connection pattern electrically connecting the pixel electrode and the TFT on the insulating layer; and a plurality of common electrodes overlapping the pixel electrode and spaced apart from one another; and metal layer patterns provided on the common electrode overlapping at least one of the data line and the gate line.

Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film.

The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.