Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide includes a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material that includes the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. An interface between a dummy gate and a gate dielectric layer of a gate-last transistor structure may be similarly formed.

Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.

Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material.

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.