A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the V.sub.F, R.sub.DSS, and BV.

A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

A semiconductor apparatus includes: a gate electrode in a trench and facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode in the trench and between the gate electrode and a bottom of the trench; an electric insulating region in the trench, the electric insulating region extending between the gate electrode and the shield electrode, and further extending along the side wall and the bottom of the trench to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n.sup.+ type source region and the shield electrode. The shield electrode has high resistance regions at positions where the high resistance regions face the side walls of the trench, and a low resistance region at a position where the low resistance region is sandwiched between the high resistance regions.

Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n.sup.+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n.sup.+ drain region side, and a low resistance region positioned on a gate electrode side.

A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n.sup.+ emitter region and an n.sup. drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n.sup.+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.