In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

A method of manufacturing a semiconductor device includes: forming field electrode structures extending in a direction vertical to a first surface in a semiconductor body; forming cell mesas from portions of the semiconductor body between the field electrode structures, including body zones forming first pn junctions with a drift zone; forming gate structures between the field electrode structures and configured to control a current flow through the body zones; and forming auxiliary diode structures with a forward voltage lower than the first pn junctions and electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.

A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.

An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.