This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N.sup.+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

A transistor device includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a drain contact adjacent the gate finger, wherein the gate finger is between the drain contact and the source contact. The device further includes a gate jumper extending in the first direction, a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar that is spaced apart from the gate bus in the first direction and that connects the gate jumper to the gate finger.

A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

A semiconductor device includes a semiconductor substrate having a first surface, first and second field plate structures extending in a first direction parallel to the first surface, a plurality of gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the second direction being different than the first direction, and a plurality of source regions and drain regions of a first conductivity type arranged in an alternating manner at the first surface so that a drain region is disposed on one side of a gate electrode structure and a source region is disposed on the other side of the gate electrode structure. The gate electrode structures are disposed between the first and the second field plate structures. The source regions and the drain regions extend in parallel with one another along the second direction.

A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.