The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first integrated circuit chip including light-emitting diodes; b) bonding a second integrated chip to a first surface of the first chip; c) decreasing the thickness of the first chip on the side opposite to the first surface to form a second surface opposite to the first surface; d) bonding, to the second surface, a cap including a silicon wafer provided with recesses opposite the light-emitting diodes; e) decreasing the thickness of the second chip; f) decreasing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) sawing the structure obtained at step f) into a plurality of separate optoelectronic devices.

A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer.

A light-emitting element is provided, including: a light-emitting unit sequentially comprising a first-type semiconductor layer, a light-emitting layer and a second-type semiconductor layer, wherein the light-emitting unit has an opening through the second-type semiconductor layer and the light-emitting layer to expose a portion of the first-type semiconductor layer; a current-conduction layer disposed on the second-type semiconductor layer; a first electrode disposed on the current-conduction layer and exposing a portion thereof; a distributed Bragg reflector disposed on the first electrode and covering the exposed portion of the current-conduction layer; and a second electrode disposed on the distributed Bragg reflector and filling the opening to electrically connect to the first-type semiconductor layer.

A light-emitting device including a semiconductor stack generating a first light, and a filter formed on the semiconductor stack, including a first surface facing the semiconductor stack and a second surface opposite to the first surface. The filter includes pairs of layers with different refractive indexes alternately stacked. A portion of the first light is transmitted by the filter. The light emitting device emits a second light including the portion of the first light, and the second light includes a first directional part with a first FWHM and a second directional part with a second FWHM smaller than the first FWHM. The first directional part has a first angle with a normal direction of the second surface in a range of 45-90 degrees and the second directional part having a second angle with the normal direction of the second surface in a range of 0-30 degrees.

A light-emitting element includes a semiconductor structure including: an n-type semiconductor layer including a first n-type semiconductor layer and a second n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The active layer is located between the n-type semiconductor layer and the p-type semiconductor layer in a thickness direction. An n-side electrode electrically connected to the n-type semiconductor layer. A p-side electrode electrically connected to the p-type semiconductor layer.

A light emitting device including a substrate, a first conductivity-type semiconductor layer, a mesa including a second conductivity-type semiconductor layer and an active layer, first and second contact electrodes respectively contacting the first and second conductivity-type semiconductor layers, a passivation layer covering the first and second contact electrodes, the mesa, and including first and second openings, and first and second bump electrodes electrically connected to the first and second contact electrodes, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, the first contact electrode includes a reflective material, and a portion of the first opening is surrounded with a side surface of the mesa, and another portion of the first opening is not surrounded with the side surface of the mesa.

High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant a.sub.substrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant a.sub.layer and [(|a.sub.substratea.sub.layer|)/a.sub.substrate]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes a semiconductor layer sequence having a bottom face and a top face, wherein the semiconductor layer sequence comprises a first layer of a first conductivity type, an active layer for generating electromagnetic radiation, and a second layer of a second conductivity type and a bottom contact element located at the bottom face and a top contact element located at the top face for injecting current into the semiconductor layer sequence. The chip further includes a current distribution element located at the bottom face, the current distribution element distributes current along the bottom face during operation and a plurality of vias extending from the current distribution element through the first layer and through the active layer into the semiconductor layer sequence, wherein the vias are not in direct electrical contact with the active layer.

Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.