A method of determining a bonding status between a wire and at least one bonding location of a workpiece is provided. The method includes the steps of: (a) bonding a portion of a wire to a bonding location of a workpiece using a bonding tool of a wire bonding machine; (b) determining a motion profile of the bonding tool for determining if the portion of the wire is bonded to the bonding location, the motion profile being configured to result in the wire being broken during the motion profile if the portion of the wire is not bonded to the bonding location; and (c) moving the bonding tool along the motion profile to determine if the portion of the wire is bonded to the bonding location. Other methods of determining a bonding status between a wire and at least one bonding location of a workpiece are also provided.

Localized stresses can be modulated in a film deposited on a bowed semiconductor substrate by selectively and locally curing the film by ultraviolet (UV) radiation. A bowed semiconductor substrate can be asymmetrically bowed. A UV-curable film is deposited on the front side or the backside of the bowed semiconductor substrate. A mask is provided between the UV-curable film and a UV source, where openings in the mask are patterned to selectively define exposed regions and non-exposed regions of the UV-curable film. Exposed regions of the UV-curable film modulate localized stresses to mitigate bowing in the bowed semiconductor substrate.

The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm.sup.-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:

Tx>Dx−Sx;

Tx<Dx−Sx+Wx2;

Tx>Sx;

Tx<Dx−Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.

The present disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a connecting element. The connecting element includes a first conductive line segment, a second conductive line segment, and a first connecting line segment. The first conductive line segment is electrically connected to the second conductive line segment through the first connecting line segment. In a vertical projection direction, the first connecting line segment has a first height, the first conductive line segment has a second height, and the first height is different from the second height.

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a support unit horizontally maintaining a substrate; a laser irradiation unit for irradiating the substrate with a laser; a photo-detector for detecting an energy of a reflective light reflected from the substrate among a laser irradiated on the substrate; and a processor, and wherein the processor irradiates a first laser of a first output to the substrate, and sets a second output of a second laser for irradiating the substrate to heat the substrate, based on an energy of a first reflective light reflected from the substrate by the first laser detected from the photo-detector.

The present disclosure relates to a latch-up test structure, including: a substrate of a first conductive type; a first well region of a second conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the second conductive type; a first doped region of the second conductive type, located in the first well region of the second conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.