A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

In various embodiments, lighting systems include an electrically insulating carrier having a plurality of conductive elements disposed thereon and a light-emitting array. The light-emitting array is disposed over the carrier and includes a plurality of light-emitting diodes (LEDs) that each has at least two electrical contacts electrically connected to conductive elements by a conductive adhesive.

Provided is a vertical type light emitting device and a method of manufacturing the same. A transparent electrode having high transmittance with respect to light in the entire range and constructed by using a resistance change material of which resistance state is to be changed from a high resistance state to a low resistance state if a voltage exceeding a threshold voltage inherent in a material is applied so that conducting filaments are formed is formed between an electrode pad and a semiconductor layer of a light emitting device. The transparent electrode has high transmittance with respect to the light in a UV wavelength range as well as in a visible wavelength range generated in the light emitting device. Since the conductivity of the transparent electrode is heightened due to the formation of the conducting filaments, the transparent electrode has good ohmic contact characteristic with respect to a semiconductor layer.

A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.

A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity. A first transistor includes a portion of the first transistor formed over the cavity.

A light emitting device package can include a sub-mount having a first surface, a second surface, a bottom surface and a cavity; a first layer on the first surface; a second layer on the second surface; a third layer on the bottom surface; a light emitting device on the first layer and including a supporting layer including an anti-diffusion layer, a first electrode on the supporting layer, a semiconductor light emitting structure electrically connected to the first electrode, and a second electrode electrically connected to the semiconductor light emitting structure, in which the first and second electrodes electrically connect to the first layer and the second layer, respectively, and the semiconductor light emitting structure includes a light extraction structure; an ESD property improving diode on the second surface, electrically connected to the second layer and arranged a distance apart from the light emitting device, and a lens on the sub-mount.

Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first metal pillar, a second metal pillar, and an insulating layer. The semiconductor layer includes a first surface, a second surface, and a light emitting layer. The first metal pillar is electrically connected to the second surface. The first metal pillar includes first and second metal layers. The first metal layer is provided between the second surface and at least a part of the second metal layer. The second metal pillar is arranged side by side with the first metal pillar, and electrically connected to the second surface. The second metal pillar includes third and fourth metal layers. The third metal layer is provided between the second surface and at least a part of the fourth metal layer. The insulating layer is provided between the first and second metal pillars.