High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a recess between the gate spacers, performing a first non-conformal deposition process to fill the recess with a first gate cap material, and planarizing the first gate cap material to remove a portion of the first gate cap material outside the recess.

A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

A semiconductor device includes a first buried gate configured to extend in a first direction, a bit-line contact disposed on one side of the first buried gate while being located outside the first buried gate, a storage node contact disposed on the other side of the first buried gate in a diagonal direction of the bit-line contact while being located outside the first buried gate, and active regions arranged spaced apart from each other in the first direction while overlapping with the first buried gate. Each active region includes a first extension region configured to extend in a second direction perpendicular to the first direction while overlapping with the bit-line contact, a second extension region configured to extend in the second direction while overlapping with the storage node contact, and a third extension region configured to extend in a diagonal direction while overlapping with the first buried gate.

A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.

A semiconductor device includes a substrate; an active region extending in a first, horizontal, direction on the substrate, and including a first active pattern at a first height above a bottom surface of the substrate in a vertical direction and having a first width in a second, horizontal, direction, a second active pattern having a second width in the second direction different from the first width, and a transition active pattern connecting the first active pattern to the second active pattern; gate structures intersecting the active region each gate structure extending in the second direction across the substrate; source/drain regions disposed on sides of the gate structures, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain region disposed on the transition active pattern. Each of the source/drain regions is disposed on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer disposed on the first epitaxial layer, at a second height above a bottom surface of the substrate in a vertical direction, a first sidewall thickness of the first epitaxial layer of the first source/drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source/drain region in the first direction, at the second height, thicknesses of opposing sidewalls of the first epitaxial layer of the transition source/drain region in the first direction are different, and a vertical level of a lowermost end of the second epitaxial layer of the first source/drain region, a vertical level of a lowermost end of the second epitaxial layer of the second source/drain region, and a vertical level of a lowermost end of the second epitaxial layer of the transition source/drain region are different from each other.