A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.

A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.