Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure comprises a semiconductor layer, a source region, a drain region, and a gate positioned between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. The first gate dielectric layer is disposed on a top surface of the semiconductor layer, and the second gate dielectric layer includes a first section on the top surface of the semiconductor layer and a second section adjacent to a sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first section of the second gate dielectric layer, and the second section of the second gate dielectric layer.

There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.

An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si.sub.3N.sub.4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO.sub.2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO.sub.2. The two SiO.sub.2 layers together form a blocking oxide layer.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.